The present invention is related to an improvement in capacitor arrays and to an improved method for making capacitor arrays.
Miniaturization is an ongoing desire in the electronics industry. This desire is driven by consumer demands for smaller, more functional, devices with decreased size and weight. This demand is contrary to the demand for decreased cost.
A perplexing problem, which is inherent in miniaturization, is the increase in parasitic electrical characteristics that plague circuitry. Even as components themselves can be improved there are physical barriers when these components are attached to a circuit board that negate some of the electrical improvements provided by the discrete components themselves. Related specifically to the issues of parasitic electrical characteristics, as discrete components, capacitors are typically attached individually to a circuit or package and when attached they require two things; space and electrical connection. As components become smaller the space between them to account for handling capabilities, and tolerances, to ensure they do not touch become a large percentage of the total circuit footprint. This introduces poor efficiency in space utilization and causes unwanted electrical performance. Prior teachings, such as commonly assigned U.S. Pat. No. 7,745,281, which is incorporated herein by reference, create advantages in the performance of capacitor miniaturization and manufacturing. While this art teaches methods for creating capacitors capable of being embedded, and capacitor manufacturing methods that include forming groups of discrete capacitors, it is the purpose of this invention to teach methods that utilize miniaturization techniques to create usefulness while avoiding many of the described issues that arise with discrete capacitors.
As the part size decreases, the manufacturing system necessary to place a large number of very small parts on a circuit becomes more complex as does the equipment required to bond the component to a circuit. The increased handling complexity can easily result in cost increases which could be many multiples above the material savings gained through the miniaturization. Related to the issue of cost, handling individual components requires expensive equipment. This cost is multiplied when the need to handle large quantities of components is complicated by the ever increasing desire to increase the handling speed of the components. Methods of creating arrays of capacitors have been seen in prior art and exist as industry practices as taught by Donghang in U.S. Pat. No. 6,324,048, which is incorporated herein by reference. These techniques can be used to create arrays and groups of capacitors but these capacitors are of very low capacitance. It will be the purpose of this invention to differentiate from these methods by the use of valve metal and the techniques to create close packed arrays of high capacitance capacitors.
The instant invention addresses ways of avoiding some of the prior pitfalls in miniaturization technologies, specifically those which relate to non-discrete capacitors, more specifically, but not limiting to the scope of this invention, valve metal capacitors that fit the criteria of being embeddable or incorporated into packaging or substrate which houses more than just discrete capacitors or capacitor elements. While the term embedded in the industry, specifically capacitors, describe a capacitor that is incorporated into a substrate, typically a printed circuit board, for purposes of simplification in the present invention the term should be understood to include any capacitor device that is incorporated into another package or substrate, with or without its own packaging.
Capacitor arrays have been described in the art with the cathode component being formed within isolation areas or dams. As the demand for further miniaturization has continued the electrical parasitics in such devices has proven to be detrimental. It has now been determined that the prior art devices exhibit migration, or wicking, of cathode components under the insolation dams thereby resulting in the formation of electrical parasitics which limited the minimum size available.
The present invention provides an improved capacitor array wherein parasitic electrical characteristics can be minimized thereby allowing for closer packing. The present invention also provides an improved method for manufacturing an array of capacitors.